Networks on chips: technology and tools
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Amsterdam [u.a.]
Elsevier
2006
|
| Series: | The Morgan Kaufmann series in systems on silicon
|
| Subjects: | |
| Links: | http://www.loc.gov/catdir/toc/ecip0615/2006018657.html http://www.loc.gov/catdir/enhancements/fy0661/2006018657-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015679320&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Item Description: | Includes bibliographical references and index |
| Physical Description: | x, 395 p. Ill., graph. Darst. 25 cm |
| ISBN: | 0123705215 9780123705211 |
Staff View
MARC
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Record in the Search Index
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|---|---|
| adam_text | Contents
About the Authors ix
List of Contributors xi
1 Networks on Chip 1
1.1 Why On Chip Networking? 2
1.2 Technology Trends 3
1.3 SoC Objectives and NoC Needs 8
1.4 Once Over Lightly 14
1.5 Perspectives 19
2 Network Architecture: Principles and Examples 23
2.1 Network Architecture 23
2.2 Network Architectures for On Chip Realization 33
2.3 Ad Hoc Network Architectures 36
2.4 Component Design for NoCs 37
2.5 Properties of Network Architectures 39
2.6 Summary 41
3 Physical Network Layer 45
3.1 Interconnection in DSM SoC 47
3.2 High Performance Signaling 52
3.3 Building Blocks 63
3.4 Summary 70
4 The Data Link Layer in NoC Design 75
4.1 Tasks of the Data Link Layer 77
4.2 On Chip Communication Reliability 79
vi Contents
4.3 Fault Models for NoCs 81
4.4 Principles of Coding Theory 89
4.5 The Power Reliability Trade Off 106
4.6 Unified Coding Framework 113
4.7 Adaptive Error Protection 117
4.8 Data Link Layer Architecture: Case Studies 121
4.9 On Chip Stochastic Communication 124
4.10 Link Level versus End to End Error Protection 126
4.11 Flow Control 131
4.12 Performance Exploration 135
4.13 Summary 139
5 Network and Transport Layers in
Network on Chip 147
5.1 Network and Transport Layers in NoCs 148
5.2 NoC QoS 152
5.3 NoC Topology 158
5.4 Switching Techniques 160
5.5 NoC Addressing and Routing 168
5.6 NoC Addressing 168
5.7 Congestion Control and Flow Control 178
5.8 Summary 195
6 Network Interface Architecture and
Design Issues 203
6.1 NI Services 206
6.2 NI Structure 210
6.3 Evolution of Communication Protocols 212
6.4 Point to Point Communication Protocols 219
6.5 Latest Advances in Processor Interfaces 233
6.6 The Packetization Stage 236
6.7 End to End Flow Control 250
6.8 Packet and Circuit Switching 253
6.9 NI Architecture: The Aethereal Case Study 257
6.10 NI Architecture: The xpipes Case Study 271
6.11 NIs for Asynchronous NoCs: The Mango Case Study 277
6.12 Summary 280
7 NoC Programming 285
7.1 Architectural Template 287
7.2 Task Level Parallel Programming 293
Contents vii
7.3 Communication Exposed Programming 308
7.4 Computer Aided Software Development Tools 315
7.5 Summary 319
8 Design Methodologies and CAD Tool
Flows for NoCs 323
8.1 Network Analysis and Simulation 325
8.2 Network Synthesis and Optimization 331
8.3 Design Flows for NoCs 333
8.4 Tool Kits for Designing Bus Based Interconnect 343
8.5 Summary 352
9 Designs and Implementations of
NoC Based SoCs 355
9.1 KAIST BONE Series 355
9.2 NoC Based Experimental Systems 379
9.3 Summary 382
Index 385
|
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| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| genre_facet | Konferenzschrift |
| id | DE-604.BV022471849 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T12:56:08Z |
| institution | BVB |
| isbn | 0123705215 9780123705211 |
| language | English |
| lccn | 2006018657 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015679320 |
| oclc_num | 70054285 |
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| owner | DE-29T DE-634 |
| owner_facet | DE-29T DE-634 |
| physical | x, 395 p. Ill., graph. Darst. 25 cm |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Elsevier |
| record_format | marc |
| series2 | The Morgan Kaufmann series in systems on silicon |
| spellingShingle | Benini, Luca Networks on chips technology and tools Réseaux d'ordinateurs - Appareils et matériel Systèmes sur une puce Systems on a chip Computer networks Equipment and supplies Netzwerk (DE-588)4171529-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4171529-9 (DE-588)4027242-4 (DE-588)1071861417 |
| title | Networks on chips technology and tools |
| title_auth | Networks on chips technology and tools |
| title_exact_search | Networks on chips technology and tools |
| title_full | Networks on chips technology and tools Luca Benini and Giovanni De Micheli |
| title_fullStr | Networks on chips technology and tools Luca Benini and Giovanni De Micheli |
| title_full_unstemmed | Networks on chips technology and tools Luca Benini and Giovanni De Micheli |
| title_short | Networks on chips |
| title_sort | networks on chips technology and tools |
| title_sub | technology and tools |
| topic | Réseaux d'ordinateurs - Appareils et matériel Systèmes sur une puce Systems on a chip Computer networks Equipment and supplies Netzwerk (DE-588)4171529-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Réseaux d'ordinateurs - Appareils et matériel Systèmes sur une puce Systems on a chip Computer networks Equipment and supplies Netzwerk Integrierte Schaltung Konferenzschrift |
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