Optimizing compilers for modern architectures: a dependence-based approach
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
San Francisco [u.a.]
Morgan Kaufmann
2002
|
| Schlagwörter: | |
| Links: | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009557063&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Beschreibung: | Hier auch später erschienene, unveränderte Nachdrucke |
| Umfang: | XXV, 790 S. graph. Darst. |
| ISBN: | 1558602860 9781558602861 |
Internformat
MARC
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| 020 | |a 1558602860 |9 1-55860-286-0 | ||
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| 100 | 1 | |a Allen, Randy |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Optimizing compilers for modern architectures |b a dependence-based approach |c Randy Allen ; Ken Kennedy |
| 264 | 1 | |a San Francisco [u.a.] |b Morgan Kaufmann |c 2002 | |
| 300 | |a XXV, 790 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Hier auch später erschienene, unveränderte Nachdrucke | ||
| 650 | 4 | |a Compilers (Computer programs) | |
| 650 | 4 | |a Compiling (Electronic computers) | |
| 650 | 4 | |a High performance computing | |
| 650 | 0 | 7 | |a Compiler |0 (DE-588)4148248-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Optimierung |0 (DE-588)4043664-0 |2 gnd |9 rswk-swf |
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| 689 | 0 | 1 | |a Optimierung |0 (DE-588)4043664-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Compiler |0 (DE-588)4148248-7 |D s |
| 689 | 1 | 1 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009557063 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0102 DAT 383f 2001 A 1153 |
|---|---|
| DE-BY-TUM_katkey | 1226899 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040070880134 040020273394 040020115666 |
| _version_ | 1821934087362838528 |
| adam_text | Contents
Preface
xvii
Chapter
1
Compiler Challenges for High-Performance Architectures
1
1.1
Overview and Goals
1
1.2
Pipelining
4
1.2.1
Pipelined Instruction Units
4
1.2.2
Pipelined Execution Units
6
1.2.3
Parallel Functional Units
7
1.2.4
Compiling for Scalar Pipelines
8
1.3
Vector Instructions
11
1.3.1
Vector Hardware Overview
11
1.3.2
Compiling for Vector Pipelines
12
1.4
Superscalar and VLIW Processors
14
1.4.1
Multiple-Issue Instruction Units
14
1.4.2
Compiling for Multiple-Issue Processors
15
1.5
Processor Parallelism
17
1.5.1
Overview of Processor Parallelism
17
1.5.2
Compiling for Asynchronous Parallelism
19
1.6
Memory Hierarchy
21
1.6.1
Overview of Memory Systems
21
1.6.2
Compiling for Memory Hierarchy
22
1.7
A Case Study: Matrix Multiplication
23
1.8
Advanced Compiler Technology
28
1.8.1
Dependence
28
1.8.2
Transformations
30
1.9
Summary
31
1.10
Casestudies
31
1.11
Historical Comments and References
32
Exercises
33
VII
Contents
Chapter
2
Dependence: Theory and Practice
35
2.1
Introduction
35
2.2
Dependence and Its Properties
36
2.2.1
Load-Store Classification
37
2.2.2
Dependence in Loops
38
2.2.3
Dependence and Transformations
41
2.2.4
Distance and Direction Vectors
45
2.2.5
Loop-Carried and Loop-Independent Dependences
49
2.3
Simple Dependence Testing
56
2.4
Parallelization and Vectorization
59
2.4.1
Parallelization
59
2.4.2
Vectorization
60
2.4.3
An Advanced Vectorization Algorithm
63
2.5
Summary
69
2.6
Case Studies
70
2.7
Historical Comments and References
70
Exercises
71
Chapter
3
Dependence Testing
73
3.1
Introduction
73
3.1.1
Background and Terminology
74
3.2
Dependence Testing Overview
79
3.2.1
Subscript Partitioning
80
3.2.2
Merging Direction Vectors
81
3.3
Single-Subscript Dependence Tests
81
3.3.1
ZIVTest
82
3.3.2
SIV
Tests
82
3.3.3
Multiple Induction-Variable Tests
94
3.4
Testing in Coupled Groups
111
3.4.1
The Delta Test
112
3.4.2
More Powerful Multiple-Subscript Tests
120
3.5
An Empirical Study
121
3.6
Putting It All Together
123
3.7
Summary
129
3.8
Casestudies
130
3.9
Historical Comments and References
131
Exercises
132
Chapter
4
Preliminary Transformations
135
4.1
Introduction
135
4.2
Information Requirements
138
Contents
4.3
Loop Normalization
138
4.4
Data Flow Analysis
141
4.4.1
Definition-Use Chains
142
4.4.2
Dead Code Elimination
145
4.4.3
Constant Propagation
146
4.4.4
Static Single-Assignment Form
148
4.5
Induction-Variable Exposure
155
4.5.1
Forward Expression Substitution
156
4.5.2
Induction-Variable Substitution
158
4.5.3
Driving the Substitution Process
162
4.6
Summary
166
4.7
Casestudies
167
4.8
Historical Comments and References
168
Exercises
169
Chapters Enhancing Fine-Grained Parallelism
171
5.1
Introduction
171
5.2
Loop Interchange
173
5.2.1
Safety of Loop Interchange
174
5.2.2
Profitability of Loop Interchange
177
5.2.3
Loop Interchange and Vectorization
179
5.3
Scalar Expansion
184
5.4
Scalar and Array Renaming
195
5.5
Node Splitting
202
5.6
Recognition of Reductions
205
5.7
Index-Set Splitting
209
5.7.1
Threshold Analysis
209
5.7.2
Loop Peeling
211
5.7.3
Section-Based Splitting
212
5.8
Run-Time Symbolic Resolution
214
5.9
Loop Skewing
216
5.10
Putting It All Together
221
5.11
Complications of Real Machines
226
5.12
Summary
230
5.13
Casestudies
231
5.13.1
PFC
231
5.13.2
Ardent Titan Compiler
232
5.13.3
Vectorization Performance
234
5.14
Historical Comments and References
236
Exercises
237
Contents
Chapter
6
Creating Coarse-Grained Parallelism
239
6.1
Introduction
239
6.2
Single-Loop Methods
240
6.2.1
Privatization
240
6.2.2
Loop Distribution
245
6.2.3
Alignment
246
6.2.4
Code Replication
249
6.2.5
Loop Fusion
254
6.3
Perfect Loop Nests
271
6.3.1
Loop Interchange for Parallelization
271
6.3.2
Loop Selection
275
6.3.3
Loop Reversal
279
6.3.4
Loop Skewing for Parallelization
280
6.3.5
Unimodular Transformations
284
6.3.6
Profitability-Based Parallelization Methods
285
6.4
Imperfectly Nested Loops
288
6.4.1
Multilevel Loop Fusion
289
6.4.2
A Parallel Code Generation Algorithm
292
6.5
An Extended Example
297
6.6
Packaging of Parallelism
298
6.6.1
Strip Mining
300
6.6.2
Pipeline Parallelism
301
6.6.3
Scheduling Parallel Work
304
6.6.4
Guided Self-Scheduling
306
6.7
Summary
309
6.8
Casestudies
310
6.8.1
PFC and ParaScope
310
6.8.2
Ardent Titan Compiler
311
6.9
Historical Comments and References
315
Exercises
316
Chapter
7
Handling Control Flow
319
7.1
Introduction
319
7.2
If-Conversion
320
7.2.1
Definition
321
7.2.2
Branch Classification
322
7.2.3
Forward Branches
323
7.2.4
Exit Branches
327
7.2.5
Backward Branches
333
7.2.6
Complete Forward Branch Removal
336
7.2.7
Simplification
338
Contents
7.2.8 Iterative
Dependences
343
7.2.9
If-Reconstruction
348
7.3
Control Dependence
350
7.3.1
Constructing Control Dependence
352
7.3.2
Control Dependence in Loops
355
7.3.3
An Execution Model for Control Dependences
356
7.3.4
Application of Control Dependence to Parallelization
359
7.4
Summary
376
7.5
Case Studies
376
7.6
Historical Comments and References
377
Exercises
378
Chapter
8
Improving Register Usage
381
8.1
Introduction
381
8.2
Scalar Register Allocation
381
8.2.1
Data Dependence for Register Reuse
383
8.2.2
Loop-Carried and Loop-Independent Reuse
384
8.2.3
A Register Allocation Example
386
8.3
Scalar Replacement
387
8.3.1
Pruning the Dependence Graph
387
8.3.2
Simple Replacement
392
8.3.3
Handling Loop-Carried Dependences
392
8.3.4
Dependences Spanning Multiple Iterations
393
8.3.5
Eliminating Scalar Copies
394
8.3.6
Moderating Register Pressure
395
8.3.7
Scalar Replacement Algorithm
396
8.3.8
Experimental Data
400
8.4
Unroll-and-Jam
403
8.4.1
Legality of Unroll-and-Jam
406
8.4.2
Unroll-and-Jam Algorithm
409
8.4.3
Effectiveness of Unroll-and-Jam
412
8.5
Loop Interchange for Register Reuse
415
8.5.1
Considerations for Loop Interchange
417
8.5.2
Loop Interchange Algorithm
419
8.6
Loop Fusion for Register Reuse
420
8.6.1
Profitable Loop Fusion for Reuse
421
8.6.2
Loop Alignment for Fusion
424
8.6.3
Fusion Mechanics
428
8.6.4
A Weighted Loop Fusion Algorithm
434
8.6.5
Multilevel Loop Fusion for Register Reuse
450
Contents
8.7
Putting It All Together
453
8.7.1
Ordering the Transformations
453
8.7.2
An Example: Matrix Multiplication
454
8.8
Complex Loop Nests
456
8.8.1
Loops with If Statements
457
8.8.2
Trapezoidal Loops
459
8.9
Summary
465
8.10
Case Studies
465
8.11
Historical Comments and References
466
Exercises
467
Chapter
9
Managing Cache
469
9.1
Introduction
469
9.2
Loop Interchange for Spatial Locality
471
9.3
Blocking
477
9.3.1
Unaligned Data
478
9.3.2
Legality of Blocking
480
9.3.3
Profitability of Blocking
482
9.3.4
A Simple Blocking Algorithm
483
9.3.5
Blocking with Skewing
485
9.3.6
Fusion and Alignment
486
9.3.7
Blocking in Combination with Other Transformations
489
9.3.8
Effectiveness
490
9.4
Cache Management in Complex Loop Nests
491
9.4.1
Triangular Cache Blocking
491
9.4.2
Special-Purpose Transformations
492
9.5
Software Prefetching
495
9.5.1
A Software Prefetching Algorithm
496
9.5.2
Effectiveness of Software Prefetching
506
9.6
Summary
507
9.7
Case Studies
508
9.8
Historical Comments and References
509
Exercises
510
Chapter
10
Scheduling
511
10.1
Introduction
511
10.2
Instruction Scheduling
512
10.2.1
Machine Model
514
10.2.2
Straight-Line Graph Scheduling
515
10.2.3
List Scheduling
516
10.2.4
Trace Scheduling
518
10.2.5
Scheduling in Loops
524
Contents xiii
10.3
Vector
Unit Scheduling
536
10.3.1
Chaining
537
10.3.2
Coprocessors
540
10.4
Summary
543
10.5
Casestudies
543
10.6
Historical Comments and References
546
Exercises
547
Chapter
11
Interprocedural Analysis and Optimization
549
11.1
Introduction
549
11.2
Interprocedural Analysis
550
11.2.1
Interprocedural Problems
550
11.2.2
Interprocedural Problem Classification
556
11.2.3
Flow-Insensitive Side Effect Analysis
560
11.2.4
Flow-Insensitive Alias Analysis
568
11.2.5
Constant Propagation
573
11.2.6
Kill Analysis
578
11.2.7
Symbolic Analysis
581
11.2.8
Array Section Analysis
585
11.2.9
Call Graph Construction
588
11.3
Interprocedural Optimization
592
11.3.1
Inline Substitution
592
11.3.2
Procedure Cloning
594
11.3.3
Hybrid Optimizations
595
11.4
Managing Whole-Program Compilation
595
11.5
Summary
599
11.6
Casestudies
600
11.7
Historical Comments and References
602
Exercises
604
Chapter
12
Dependence in
С
and Hardware Design
605
12.1
Introduction
605
12.2
Optimizing
С
606
12.2.1
Pointers
608
12.2.2
Naming and Structures
610
12.2.3
Loops
612
12.2.4
Scoping and Statics
613
12.2.5
Dialect
613
12.2.6
Miscellaneous
615
12.3
Hardware Design
617
12.3.1
Hardware Description Languages
619
12.3.2
Optimizing Simulation
622
12.3.3
Synthesis Optimization
639
Contents
12.4
Summary
651
12.5
Casestudies
652
12.6
Historical Comments and References
652
Exercises
653
Chapter
13
Compiling Array Assignments
655
13.1
Introduction
655
13.2
Simple Scalarization
656
13.3
Scalarization Transformations
660
13.3.1
Loop Reversal
660
13.3.2
Input Prefetching
661
13.3.3
Loop Splitting
666
13.4
Multidimensional Scalarization
668
13.4.1
Simple Scalarization in Multiple Dimensions
670
13.4.2
Outer Loop Prefetching
671
13.4.3
Loop Interchange for Scalarization
674
13.4.4
General Multidimensional Scalarization
677
13.4.5
A Scalarization Example
681
13.5
Considerations for Vector Machines
683
13.6
Postscalarization Interchange and Fusion
684
13.7
Summary
686
13.8
Casestudies
687
13.9
Historical Comments and References
687
Exercises
688
Chapter
14
Compiling High Performance Fortran
689
14.1
Introduction
689
14.2
HPF Compiler Overview
694
14.3
Basic Loop Compilation
698
14.3.1
Distribution Propagation and Analysis
698
14.3.2
Iteration Partitioning
700
14.3.3
Communication Generation
704
14.4
Optimization
710
14.4.1
Communication Vectorization
710
14.4.2
Overlapping Communication and Computation
716
14.4.3
Alignment and Replication
717
14.4.4
Pipelining
719
14.4.5
Identification of Common Recurrences
721
14.4.6
Storage Management
722
14.4.7
Handling Multiple Dimensions
726
Contents
14.5 Interprocedural
Optimization for HPF
728
14.6
Summary
729
14.7
Case Studies
730
14.8
Historical Comments and References
732
Exercises
733
Appendix Fundamentals of Fortran
90 735
Introduction
735
Lexical Properties
735
Array Assignment
736
Library Functions
741
Further Reading
742
References
743
Index
765
|
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| author | Allen, Randy Kennedy, Ken |
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| id | DE-604.BV013963968 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:56:42Z |
| institution | BVB |
| isbn | 1558602860 9781558602861 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009557063 |
| oclc_num | 48396100 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-739 DE-29T DE-703 DE-634 DE-473 DE-BY-UBG |
| owner_facet | DE-91G DE-BY-TUM DE-739 DE-29T DE-703 DE-634 DE-473 DE-BY-UBG |
| physical | XXV, 790 S. graph. Darst. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Morgan Kaufmann |
| record_format | marc |
| spellingShingle | Allen, Randy Kennedy, Ken Optimizing compilers for modern architectures a dependence-based approach Compilers (Computer programs) Compiling (Electronic computers) High performance computing Compiler (DE-588)4148248-7 gnd Computerarchitektur (DE-588)4048717-9 gnd Optimierung (DE-588)4043664-0 gnd |
| subject_GND | (DE-588)4148248-7 (DE-588)4048717-9 (DE-588)4043664-0 |
| title | Optimizing compilers for modern architectures a dependence-based approach |
| title_auth | Optimizing compilers for modern architectures a dependence-based approach |
| title_exact_search | Optimizing compilers for modern architectures a dependence-based approach |
| title_full | Optimizing compilers for modern architectures a dependence-based approach Randy Allen ; Ken Kennedy |
| title_fullStr | Optimizing compilers for modern architectures a dependence-based approach Randy Allen ; Ken Kennedy |
| title_full_unstemmed | Optimizing compilers for modern architectures a dependence-based approach Randy Allen ; Ken Kennedy |
| title_short | Optimizing compilers for modern architectures |
| title_sort | optimizing compilers for modern architectures a dependence based approach |
| title_sub | a dependence-based approach |
| topic | Compilers (Computer programs) Compiling (Electronic computers) High performance computing Compiler (DE-588)4148248-7 gnd Computerarchitektur (DE-588)4048717-9 gnd Optimierung (DE-588)4043664-0 gnd |
| topic_facet | Compilers (Computer programs) Compiling (Electronic computers) High performance computing Compiler Computerarchitektur Optimierung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009557063&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT allenrandy optimizingcompilersformodernarchitecturesadependencebasedapproach AT kennedyken optimizingcompilersformodernarchitecturesadependencebasedapproach |
Inhaltsverzeichnis
Paper/Kapitel scannen lassen
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 DAT 383f 2001 A 1153
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |
| Exemplar 2 | Ausleihbar Am Standort |
| Exemplar 3 | Ausleihbar Am Standort |