Timing analysis and optimization of sequential circuits:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1999
|
| Schlagwörter: | |
| Umfang: | XV, 190 S. graph. Darst. |
| ISBN: | 0792383214 |
Internformat
MARC
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| 100 | 1 | |a Maheshwari, Naresh |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Timing analysis and optimization of sequential circuits |c Naresh Maheshwari ; Sachin S. Sapatnekar |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1999 | |
| 300 | |a XV, 190 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Circuits intégrés à très grande échelle - Conception et construction - Informatique | |
| 650 | 4 | |a Computer-aided design | |
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| 650 | 4 | |a Integrated circuits - Very large scale integration - Design and construction - Data processing | |
| 650 | 4 | |a Série chronologique - Informatique | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design | |
| 650 | 4 | |a Time-series analysis |x Data processing | |
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| 700 | 1 | |a Sapatnekar, Sachin S. |e Verfasser |4 aut | |
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Datensatz im Suchindex
| DE-BY-TUM_call_number | 0001 2000 A 93 |
|---|---|
| DE-BY-TUM_katkey | 1119749 |
| DE-BY-TUM_location | Mag |
| DE-BY-TUM_media_number | 040003697516 |
| _version_ | 1821931586667413504 |
| any_adam_object | |
| author | Maheshwari, Naresh Sapatnekar, Sachin S. |
| author_facet | Maheshwari, Naresh Sapatnekar, Sachin S. |
| author_role | aut aut |
| author_sort | Maheshwari, Naresh |
| author_variant | n m nm s s s ss sss |
| building | Verbundindex |
| bvnumber | BV012669910 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
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| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_tum | ELT 459f |
| ctrlnum | (OCoLC)39739773 (DE-599)BVBBV012669910 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV012669910 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:34:19Z |
| institution | BVB |
| isbn | 0792383214 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008610396 |
| oclc_num | 39739773 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM |
| owner_facet | DE-29T DE-91 DE-BY-TUM |
| physical | XV, 190 S. graph. Darst. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Kluwer |
| record_format | marc |
| spellingShingle | Maheshwari, Naresh Sapatnekar, Sachin S. Timing analysis and optimization of sequential circuits Circuits intégrés à très grande échelle - Conception et construction - Informatique Computer-aided design Conception assistée par ordinateur Integrated circuits - Very large scale integration - Design and construction - Data processing Série chronologique - Informatique Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Time-series analysis Data processing Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd |
| subject_GND | (DE-588)4052057-2 (DE-588)4131023-8 |
| title | Timing analysis and optimization of sequential circuits |
| title_auth | Timing analysis and optimization of sequential circuits |
| title_exact_search | Timing analysis and optimization of sequential circuits |
| title_full | Timing analysis and optimization of sequential circuits Naresh Maheshwari ; Sachin S. Sapatnekar |
| title_fullStr | Timing analysis and optimization of sequential circuits Naresh Maheshwari ; Sachin S. Sapatnekar |
| title_full_unstemmed | Timing analysis and optimization of sequential circuits Naresh Maheshwari ; Sachin S. Sapatnekar |
| title_short | Timing analysis and optimization of sequential circuits |
| title_sort | timing analysis and optimization of sequential circuits |
| topic | Circuits intégrés à très grande échelle - Conception et construction - Informatique Computer-aided design Conception assistée par ordinateur Integrated circuits - Very large scale integration - Design and construction - Data processing Série chronologique - Informatique Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Time-series analysis Data processing Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Conception et construction - Informatique Computer-aided design Conception assistée par ordinateur Integrated circuits - Very large scale integration - Design and construction - Data processing Série chronologique - Informatique Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Time-series analysis Data processing Schaltwerk Logische Schaltung |
| work_keys_str_mv | AT maheshwarinaresh timinganalysisandoptimizationofsequentialcircuits AT sapatnekarsachins timinganalysisandoptimizationofsequentialcircuits |
Paper/Kapitel scannen lassen
Bibliotheksmagazin
| Signatur: |
0001 2000 A 93 Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |