HDL chip design: a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Madison, AL
Doone
1998
|
| Ausgabe: | 5. print., minor rev. |
| Schlagwörter: | |
| Umfang: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Internformat
MARC
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| 041 | 0 | |a eng | |
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| 050 | 0 | |a TK7874.6 .S62 1996 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith |
| 250 | |a 5. print., minor rev. | ||
| 264 | 1 | |a Madison, AL |b Doone |c 1998 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Design and construction |x Data processing | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Field programmable gate arrays |x Design and construction |x Data processing | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 689 | 2 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 2 | |8 2\p |5 DE-604 | |
| 689 | 3 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 3 | |8 3\p |5 DE-604 | |
| 689 | 4 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 4 | |8 4\p |5 DE-604 | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 4\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-008354191 | |
Datensatz im Suchindex
| _version_ | 1818954819487924224 |
|---|---|
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV012322411 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.6 .S62 1996 |
| callnumber-search | TK7874.6 .S62 1996 |
| callnumber-sort | TK 47874.6 S62 41996 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)606049435 (DE-599)BVBBV012322411 |
| discipline | Informatik |
| edition | 5. print., minor rev. |
| format | Book |
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| id | DE-604.BV012322411 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:28:14Z |
| institution | BVB |
| isbn | 0965193438 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008354191 |
| oclc_num | 606049435 |
| open_access_boolean | |
| owner | DE-Aug4 |
| owner_facet | DE-Aug4 |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
| publishDateSort | 1998 |
| publisher | Doone |
| record_format | marc |
| spelling | Smith, Douglas J. Verfasser aut HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith 5. print., minor rev. Madison, AL Doone 1998 XVI, 448 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Application specific integrated circuits Design and construction Data processing Computer-aided design Field programmable gate arrays Design and construction Data processing Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf VHDL (DE-588)4254792-1 s DE-604 Hardwarebeschreibungssprache (DE-588)4159102-1 s 1\p DE-604 Kundenspezifische Schaltung (DE-588)4122250-7 s 2\p DE-604 VERILOG (DE-588)4268385-3 s 3\p DE-604 Field programmable gate array (DE-588)4347749-5 s 4\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Datenverarbeitung Application specific integrated circuits Design and construction Data processing Computer-aided design Field programmable gate arrays Design and construction Data processing Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) Kundenspezifische Schaltung (DE-588)4122250-7 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4347749-5 (DE-588)4268385-3 (DE-588)4254792-1 (DE-588)4159102-1 |
| title | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_fullStr | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_full_unstemmed | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing synthesizing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Datenverarbeitung Application specific integrated circuits Design and construction Data processing Computer-aided design Field programmable gate arrays Design and construction Data processing Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) Kundenspezifische Schaltung (DE-588)4122250-7 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd |
| topic_facet | Datenverarbeitung Application specific integrated circuits Design and construction Data processing Computer-aided design Field programmable gate arrays Design and construction Data processing Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) Kundenspezifische Schaltung Field programmable gate array VERILOG VHDL Hardwarebeschreibungssprache |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsynthesizingandsimulatingasicsandfpgasusingvhdlorverilog |