VHDL: a logic synthesis approach
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
London [u.a.]
Chapman & Hall
1997
|
| Schlagwörter: | |
| Umfang: | X, 339 S. grraph. Darst. |
| ISBN: | 0412616505 |
Internformat
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| 100 | 1 | |a Naylor, David |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a VHDL |b a logic synthesis approach |c David Naylor and Simon Jones |
| 264 | 1 | |a London [u.a.] |b Chapman & Hall |c 1997 | |
| 300 | |a X, 339 S. |b grraph. Darst. | ||
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| 650 | 4 | |a Datenverarbeitung | |
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| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 700 | 1 | |a Jones, Simon |e Verfasser |4 aut | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007881272 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0102 DAT 370f 2001 A 26131 |
|---|---|
| DE-BY-TUM_katkey | 879122 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040020205665 |
| _version_ | 1821931242771185664 |
| any_adam_object | |
| author | Naylor, David Jones, Simon |
| author_facet | Naylor, David Jones, Simon |
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| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV011688870 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T10:16:57Z |
| institution | BVB |
| isbn | 0412616505 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007881272 |
| oclc_num | 37413688 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | X, 339 S. grraph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Chapman & Hall |
| record_format | marc |
| spellingShingle | Naylor, David Jones, Simon VHDL a logic synthesis approach Datenverarbeitung Computer-aided design Logic design Data processing VHDL (Computer hardware description language) |
| title | VHDL a logic synthesis approach |
| title_auth | VHDL a logic synthesis approach |
| title_exact_search | VHDL a logic synthesis approach |
| title_full | VHDL a logic synthesis approach David Naylor and Simon Jones |
| title_fullStr | VHDL a logic synthesis approach David Naylor and Simon Jones |
| title_full_unstemmed | VHDL a logic synthesis approach David Naylor and Simon Jones |
| title_short | VHDL |
| title_sort | vhdl a logic synthesis approach |
| title_sub | a logic synthesis approach |
| topic | Datenverarbeitung Computer-aided design Logic design Data processing VHDL (Computer hardware description language) |
| topic_facet | Datenverarbeitung Computer-aided design Logic design Data processing VHDL (Computer hardware description language) |
| work_keys_str_mv | AT naylordavid vhdlalogicsynthesisapproach AT jonessimon vhdlalogicsynthesisapproach |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 DAT 370f 2001 A 26131
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |