HDL chip design: a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Madison, AL
Doone
1996
|
| Schlagwörter: | |
| Umfang: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV011202286 | ||
| 003 | DE-604 | ||
| 005 | 19980114 | ||
| 007 | t| | ||
| 008 | 970214s1996 xx d||| |||| 00||| eng d | ||
| 020 | |a 0965193438 |9 0-9651934-3-8 | ||
| 035 | |a (OCoLC)35553898 | ||
| 035 | |a (DE-599)BVBBV011202286 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 |a DE-898 | ||
| 050 | 0 | |a TK7874.6 | |
| 082 | 0 | |a 621.39/5 |2 21 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith |
| 264 | 1 | |a Madison, AL |b Doone |c 1996 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Circuits intégrés à la demande - Conception et construction - Informatique | |
| 650 | 4 | |a Conception assistée par ordinateur | |
| 650 | 4 | |a Réseaux logiques programmables par l'utilisateur - Conception et construction - Informatique | |
| 650 | 4 | |a Structure logique - Informatique | |
| 650 | 4 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 4 | |a Verilog (Langage de description de matériel informatique) | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Computer-aided design | |
| 650 | 4 | |a Field programmable gate arrays |x Computer-aided design | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 2 | |8 1\p |5 DE-604 | |
| 689 | 3 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 3 | |8 2\p |5 DE-604 | |
| 689 | 4 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 4 | |8 3\p |5 DE-604 | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007513355 | |
Datensatz im Suchindex
| _version_ | 1818953553955258368 |
|---|---|
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV011202286 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.6 |
| callnumber-search | TK7874.6 |
| callnumber-sort | TK 47874.6 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)35553898 (DE-599)BVBBV011202286 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV011202286 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:08:07Z |
| institution | BVB |
| isbn | 0965193438 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007513355 |
| oclc_num | 35553898 |
| open_access_boolean | |
| owner | DE-Aug4 DE-898 DE-BY-UBR |
| owner_facet | DE-Aug4 DE-898 DE-BY-UBR |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Doone |
| record_format | marc |
| spelling | Smith, Douglas J. Verfasser aut HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith Madison, AL Doone 1996 XVI, 448 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Circuits intégrés à la demande - Conception et construction - Informatique Conception assistée par ordinateur Réseaux logiques programmables par l'utilisateur - Conception et construction - Informatique Structure logique - Informatique VHDL (Langage de description de matériel informatique) Verilog (Langage de description de matériel informatique) Datenverarbeitung Application specific integrated circuits Computer-aided design Field programmable gate arrays Computer-aided design Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 s DE-604 VHDL (DE-588)4254792-1 s Kundenspezifische Schaltung (DE-588)4122250-7 s 1\p DE-604 VERILOG (DE-588)4268385-3 s 2\p DE-604 Field programmable gate array (DE-588)4347749-5 s 3\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Circuits intégrés à la demande - Conception et construction - Informatique Conception assistée par ordinateur Réseaux logiques programmables par l'utilisateur - Conception et construction - Informatique Structure logique - Informatique VHDL (Langage de description de matériel informatique) Verilog (Langage de description de matériel informatique) Datenverarbeitung Application specific integrated circuits Computer-aided design Field programmable gate arrays Computer-aided design Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4122250-7 (DE-588)4347749-5 (DE-588)4159102-1 (DE-588)4254792-1 |
| title | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_fullStr | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_full_unstemmed | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing synthesizing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Circuits intégrés à la demande - Conception et construction - Informatique Conception assistée par ordinateur Réseaux logiques programmables par l'utilisateur - Conception et construction - Informatique Structure logique - Informatique VHDL (Langage de description de matériel informatique) Verilog (Langage de description de matériel informatique) Datenverarbeitung Application specific integrated circuits Computer-aided design Field programmable gate arrays Computer-aided design Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Circuits intégrés à la demande - Conception et construction - Informatique Conception assistée par ordinateur Réseaux logiques programmables par l'utilisateur - Conception et construction - Informatique Structure logique - Informatique VHDL (Langage de description de matériel informatique) Verilog (Langage de description de matériel informatique) Datenverarbeitung Application specific integrated circuits Computer-aided design Field programmable gate arrays Computer-aided design Logic design Data processing VHDL (Computer hardware description language) Verilog (Computer hardware description language) VERILOG Kundenspezifische Schaltung Field programmable gate array Hardwarebeschreibungssprache VHDL |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsynthesizingandsimulatingasicsandfpgasusingvhdlorverilog |