Simplicity versus accuracy in a model of cache coherency overhead - Eggers, Susan J. (1989)
Abstract: "This paper analyzes which factors are important to consider when building a model of coherency overhead for a single-bus, shared memory multiprocessor. Three architectural features are examined: (1) the size of the coherency block, (2) cache size and (3) the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively including it in a base model and then comparing the model's predictions of coherency overhead to the results of realistic multiprocessor simulations. The results indicate that coherency block size is critical to include in a model of coherency overhead
Keywords: Cache memory; Multiprocessors