High level synthesis of ASICs under timing and synchronization constraints:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boston u.a.
Kluwer Acad. Publ.
1992
|
| Series: | The Kluwer international series in engineering and computer science
177.: VLSI, computer architecture and digital signal processing |
| Subjects: | |
| Physical Description: | XIII, 294 S. graph. Darst. |
| ISBN: | 0792392442 |
Staff View
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
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| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381/5 |
| dewey-search | 621.381/5 |
| dewey-sort | 3621.381 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV006607312 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T08:51:37Z |
| institution | BVB |
| isbn | 0792392442 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-004220885 |
| oclc_num | 25628783 |
| open_access_boolean | |
| owner | DE-29T DE-739 DE-83 |
| owner_facet | DE-29T DE-739 DE-83 |
| physical | XIII, 294 S. graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Kluwer Acad. Publ. |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Ku, David C. Verfasser aut High level synthesis of ASICs under timing and synchronization constraints by David C. Ku and Giovanni de Micheli Boston u.a. Kluwer Acad. Publ. 1992 XIII, 294 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 177.: VLSI, computer architecture and digital signal processing Circuits intégrés ram Ordinateurs ram synthèse circuit inriac Application specific integrated circuits Computer-aided design Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 De Micheli, Giovanni 1955- Verfasser (DE-588)114063575 aut The Kluwer international series in engineering and computer science 177.: VLSI, computer architecture and digital signal processing (DE-604)BV023545171 177 |
| spellingShingle | Ku, David C. De Micheli, Giovanni 1955- High level synthesis of ASICs under timing and synchronization constraints The Kluwer international series in engineering and computer science Circuits intégrés ram Ordinateurs ram synthèse circuit inriac Application specific integrated circuits Computer-aided design Schaltungsentwurf (DE-588)4179389-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4122250-7 |
| title | High level synthesis of ASICs under timing and synchronization constraints |
| title_auth | High level synthesis of ASICs under timing and synchronization constraints |
| title_exact_search | High level synthesis of ASICs under timing and synchronization constraints |
| title_full | High level synthesis of ASICs under timing and synchronization constraints by David C. Ku and Giovanni de Micheli |
| title_fullStr | High level synthesis of ASICs under timing and synchronization constraints by David C. Ku and Giovanni de Micheli |
| title_full_unstemmed | High level synthesis of ASICs under timing and synchronization constraints by David C. Ku and Giovanni de Micheli |
| title_short | High level synthesis of ASICs under timing and synchronization constraints |
| title_sort | high level synthesis of asics under timing and synchronization constraints |
| topic | Circuits intégrés ram Ordinateurs ram synthèse circuit inriac Application specific integrated circuits Computer-aided design Schaltungsentwurf (DE-588)4179389-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Circuits intégrés Ordinateurs synthèse circuit Application specific integrated circuits Computer-aided design Schaltungsentwurf Kundenspezifische Schaltung |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT kudavidc highlevelsynthesisofasicsundertimingandsynchronizationconstraints AT demicheligiovanni highlevelsynthesisofasicsundertimingandsynchronizationconstraints |