Formal specification and verification in VLSI design:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Edinburgh
Edinburgh Univ. Press
1990
|
| Schriftenreihe: | Edinburgh information technology series
8 |
| Schlagwörter: | |
| Umfang: | IX, 195 S. |
| ISBN: | 0748601597 |
Internformat
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Datensatz im Suchindex
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|---|---|
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| author | Davie, Bruce S. |
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| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV004441864 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T08:18:18Z |
| institution | BVB |
| isbn | 0748601597 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002755620 |
| oclc_num | 25631748 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-739 |
| owner_facet | DE-91 DE-BY-TUM DE-739 |
| physical | IX, 195 S. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | Edinburgh Univ. Press |
| record_format | marc |
| series | Edinburgh information technology series |
| series2 | Edinburgh information technology series |
| spellingShingle | Davie, Bruce S. Formal specification and verification in VLSI design Edinburgh information technology series Integrated circuits Verification Integrated circuits Very large scale integration Computer-aided design Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4117388-0 |
| title | Formal specification and verification in VLSI design |
| title_auth | Formal specification and verification in VLSI design |
| title_exact_search | Formal specification and verification in VLSI design |
| title_full | Formal specification and verification in VLSI design Bruce S. Davie |
| title_fullStr | Formal specification and verification in VLSI design Bruce S. Davie |
| title_full_unstemmed | Formal specification and verification in VLSI design Bruce S. Davie |
| title_short | Formal specification and verification in VLSI design |
| title_sort | formal specification and verification in vlsi design |
| topic | Integrated circuits Verification Integrated circuits Very large scale integration Computer-aided design Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits Verification Integrated circuits Very large scale integration Computer-aided design Entwurf VLSI |
| volume_link | (DE-604)BV000725105 |
| work_keys_str_mv | AT daviebruces formalspecificationandverificationinvlsidesign |
Paper/Kapitel scannen lassen
Bibliotheksmagazin
| Signatur: |
0001 91 A 1767
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |